1. Field of the Invention
This invention relates to an electronic material, its manufacturing method, dielectric capacitor, nonvolatile memory and semiconductor device.
2. Description of the Related Art
Ferroelectric memory is nonvolatile memory utilizing high-speed inversion of polarization and residual polarization of a ferroelectric film and permitting high-speed rewriting. FIG. 13 shows an example of conventional ferroelectric memory.
As shown in FIG. 13, the conventional ferroelectric memory includes a field insulation film 102 selectively provided on one surface of a p-type Si substrate 10 to separate individual devices. A gate insulation film 103 is provided on the surface of an active region surrounded by the field insulation film 102. Reference symbol WL denotes a word line. An n.sup.+ -type source region 104 and a drain region 105 are provided in selective portions of the p-type Si substrate 101 at opposite sides of the word line WL. The word line WL, source region 104 and drain region 105 construct a transistor Q.
Numeral 106 denotes an inter-layer insulation film. Sequentially deposited on the inter-layer insulation film 106 above the field insulation film 102 via a Ti film 107 as a bonding layer with a thickness around 30 nm, for example, are: a Pt film 108 of a thickness around 200 nm, for example, to behave as a lower electrode, a ferroelectric film 109 made of a Pb(Zr, Ti)O.sub.3 (PZT) film or SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT) film 109 with a thickness around 200 nm, for example, and a Pt film 110 as an upper electrode with a thickness around 200 nm, for example, which all construct a capacitor C. The transistor Q and the capacitor C form one memory cell.
Numeral 111 denotes an inter-layer insulation film. A contact hole 112 is provided in the inter-layer insulation films 106 and 111 above the source region 104. Another contact hole 113 is formed in the inter-layer insulation film 111 above one end of the Pt film 108. A further contact hole 114 is provided in the inter-layer insulation film 111 above the Pt film 110. The source region 104 of the transistor Q and the Pt film 108 forming the lower electrode of the capacitor C are connected by wiring 115 through the contact holes 112 and 113. Wiring 116 is connected to the Pt film 110 as the upper electrode of the capacitor C through the contact hole 114. Numeral 117 denotes a passivation film.
In the conventional ferroelectric memory shown in FIG. 13, the transistor Q and the capacitor C are arranged laterally side-by-side (in the direction parallel to the substrate surface). However, a structure with a longitudinal (normal to the substrate surface) arrangement of the transistor Q and the capacitor C is required to increase the information recording density of the ferroelectric memory. An example designed for this purpose is shown in FIG. 14 where elements common to FIG. 13 are labelled with the same reference numerals.
In FIG. 14, WL1 through WL4 are word lines, and 118 is an inter-layer insulation film. A contact hole 119 is provided in the inter-layer insulation film 118 above the drain region 105 to connect the bit line BL to the drain region 105 of the transistor Q through the contact hole 119. Numerals 120 and 121 denote inter-layer insulation films. A contact hole 122 is provided in the inter-layer insulation film 121 above the source region 104, and a polycrystalline Si plug 123 is inlaid into the contact hole 122. The source region 104 of the transistor Q and the Pt film 108 as the lower electrode of the capacitor C are electrically connected by the polycrystalline Si plug 123.
Upon forming the ferroelectric film 109, it is usually necessary to anneal the product in an oxygen atmosphere at a temperature as high as 600 through 800.degree. C. for crystallization. During the process, however, Si of the polycrystalline Si plug 123 thermally diffuses into the Pt film 108 forming the lower electrode of the capacitor C, and is oxidized in an upper layer of the Pt film 108. Thus, the Pt film 108 results in losing its electric conductivity. Moreover, Si further diffuses into the ferroelectric film 109, and seriously deteriorates the characteristics of the capacitor C.
It has been reported that, if the ferroelectric film 109 is made of PZT whose burning temperature is around 600.degree. C., a nitride film, such as TiN, can be used as a film for preventing diffusion of Si (Japan Society of Applied Physics spiring1995, 30p-D-20, 30p-D-10). Nitride films, however, are oxidized when annealed in high-temperature oxide atmospheres, and lose electric conductivity. Therefore, when introducing a sufficient amount of oxygen into the annealing atmosphere and increasing the annealing temperature to improve the ferroelectric characteristics of the ferroelectric film 109, such oxidization causes a surface roughness and an increase in electric resistance.
On the other hand, when the ferroelectric film 109 is made of SBT, which is believed to have better fatigue characteristics than PZT, it needs an annealing temperature around 800.degree. C. higher than that of the PZT for ensuring acceptable ferroelectric characteristics. Therefore, if SBT is used as the material of the ferroelectric material 109, the diffusion preventing layer made of the above-mentioned nitride film is not resistant to the high temperature, and is not usable.
There is not report, heretofore, on a deposited capacitor structure using SBT as the material of the ferroelectric thin film 109, and it has been considered difficult to realize high-integrated nonvolatile memory using such a capacitor.
The same problems may arise also when a W plug is used in lieu of the polycrystalline Si plug.
On the other hand, there is a conventional example of very high integrated semiconductor circuit device, as shown in FIG. 15, having a multi-layered wiring structure in which minimum processing size is 0.50 to 0.35 .mu.m (for example, Nikkei Microdevice, July 1994, pp. 50-57, and Nikkei Microdevice, September 1995, pp. 70-77).
As shown in FIG. 15, in the conventional semiconductor integrated circuit device, a p well 202 and an n well 203 are provided in an n-type Si substrate 201. The n-type Si substrate 201 has a recess 204 on its surface of a portion thereof used as the device isolating region, and a field insulation film 205 made of SiO.sub.2 is inlaid into the recess 204. A gate insulation film 206 made of SiO.sub.2 is provided on the surface of the active region surrounded by the field insulation film 205. Numeral 207 denotes a polycrystalline Si film doped with an impurity, and 208 denotes a metal silicide film such as WSi.sub.x film. The polycrystalline Si film 207 and the metal silicide film 208 form a polycide-structure gate electrode. A side wall spacer 209 made of SiO.sub.2 is provided on side walls of the polycrystalline Si film 207 and the metal silicide film 208. Provided in the n well 203 are p.sup.+ -type diffused layers 210, 211 for use as a source region or a drain region in self alignment with the gate electrode made of the polycrystalline Si film 207 and the metal silicide film 208. The gate electrode and the diffused layers 210, 211 form a p-channel MOS transistor. Similarly, an n-channel MOS transistor is formed in the p well 202. Numerals 212 and 213 denote n.sup.+ -type diffused layers used as the source region or the drain region of the n-channel MOS transistor.
An inter-layer insulation film 214 is provided to cover the p-channel MOS transistor and the n-channel MOS transistor. The inter-layer insulation film 214 has connection holes 215, 216 at portions aligned with the diffused layer 211 of the p-channel MOS transistor and the gate electrode of the field insulation film 205, respectively. A W plug 219 is inlaid in these connection holes 215, 216 via a Ti film 217 and a TiN film 218.
Provided on the connection hole 215, 216 is an Al-Cu alloy wiring 222 via a Ti film 220 and a TiN film 221, and provided thereon is a TiN film 223. Numeral 224 denotes an inter-layer insulation film. The inter-layer insulation film 224 has connection holes 225, 226 at portions aligned with the Al-Cu alloy wiring 222. A W plug 229 is inlaid in these connection holes 225, 226 via a Ti film 227 and a TiN film 228.
Further provided on the connection holes 225 and 226 is an Al-Cu alloy wiring 232 via a Ti film 230 and a TiN film 231, and provided thereon is a TiN film 233.
In the semiconductor integrated circuit device shown in FIG. 15, the TiN film 217 on the diffused layer 211 (having a thickness, typically, 5 to 50 nm) at a portion of the connection hole 215 is used mainly for ensuring good electric connection between the W plug 219 and the diffused layer 211 and for improving adhesion to the underlying material, taking it into account that, since the surface of the diffused layer 211 is chemically active, a SiO.sub.x film as thin as 0.5 to 5 nm is formed on the surface in a very short time (probably less than 2 to 3 minutes) when exposed to moisture or air, and electric connection and adhesion to the diffused layer 211 and degraded. In contrast, when the Ti film 217 is provided on the diffused layer 211, chemical reaction occurs between the Ti film 217 and the SiO.sub.x film formed on the surface of the diffused layer 211, and improves the electric connection and mechanical adhesion.
However, when the W plug 219 (typically as thick as 50 to 700 nm) is formed on the diffused layer 211 via the Ti film 217, WSi.sub.x is formed by chemical reaction of Si in the diffused layer 211 and the W plug 219 during annealing for forming the W plug 219 (typically at 300 to 300.degree. C.) or during subsequent annealing (typically at 350 to 450.degree. C.). Then, due to movements of elements (mainly, Si moves from the diffused layer 211 into the W plug 219), gaps are produced between the diffused layer 211 and the W plug 219, and degrade electrical connection. Thus, in order to prevent chemical reaction between the diffused layer 2111 and the W plug 219, the TiN film 218 (typically 5 to 50 nm thick) is provided between the Ti film 217 and the W plug 219. Therefore, the TiN film 218 is called barrier metal. Also usable a TiON film as the barrier metal.
The TiN film 220 formed on the W plug 219 is used to ensure reliable electrical connection and mechanical connection between the W plug 219 and the Al-Cu alloy wiring 222. The TiN film 221 on the Ti film 220 is used to minimize movements and chemical reaction of elements between the W plug 219 and the Al-Cu alloy wiring 222. Also the Ti film 230 and the TiN film 231 formed on the W plug 229 at connection holes 225, 226 are used for the same reason.
However, in the manufacturing process of the semiconductor integrated circuit device, if the W plug 219 is formed via the Ti film 217 and the TiN film 218, then the upper limit of the process temperature in subsequent steps is limited to a value not higher than the heat-resistant temperature of the TiN film 218. Since the heat resistant temperature of the TiN film 218 is around 500.degree. C. (when using sputtering) through 650.degree. C. (when using CVD), there is substantially no freedom for selecting the process temperature and time after the W plug 219 is formed. This problem arises also when a Si plug or Al plug is used instead of the W plug 219.
For these reasons, in the case where, like the conventional ferroelectric memory shown in FIG. 14, the transistor Q and the capacitor C are aligned longitudinally so as to connect the lower electrode of the capacitor C, namely the Pt film 108, to the source region 104 of the transistor Q via the polycrystalline Si plug 123 or W plug, it has been difficult to use SBT, requiring high-temperature annealing, as the material of the ferroelectric film 109 of the capacitor C.